System designers continually push IC manufactures to design ICs, such as volatile-memory ICs, that have lower power requirements, particularly during low-power, i.e., "sleep", modes. Unfortunately, as discussed below, it is difficult for IC manufacturers to reduce the sleep-mode power consumed by ICs that include volatile memory cells.
Because the data stored in a volatile memory cell--such as a dynamic-random-access-memory (DRAM) cell--degrades relatively quickly, the data must be periodically refreshed. Therefore, an IC that includes one or more volatile memory cells periodically implements refresh cycles.
During a typical refresh cycle, a sense amplifier reads the data stored in the memory cell and then writes the same data back into the cell. More specifically, the cell stores a signal level, such as a voltage level, that represents the value of the stored data. For example, a voltage level of Vdd often represents a data value of logic 1, and a voltage level of ground (0 V) often represents a data value of logic 0. Unfortunately, well-known phenomena such as memory-cell leakage cause this signal level to decay over time. If this signal level is not maintained, then It may decay to a point where it represents a data value different than the data value originally stored in the memory cell. For example, a voltage level of Vdd (logic 1) may decay toward 0 V (logic 0), and if not maintained, may eventually become close enough to 0 V to represent logic 0 instead of logic 1. To maintain the stored signal level, the IC containing the memory cell implements a refresh cycle during which the sense amplifier receives the signal level from the cell, amplifies the signal level to its full value (Le., Vdd for logic 1 and 0 V for logic 0), and provides the full signal level to the cell for storage.
During normal operation of an IC that contains a volatile memory cell, the electronic system incorporating the IC periodically issues an auto-refresh command to refresh the cell. For example, the IC may include multiple rows of memory cells and a refresh address counter that indicates the row to be refreshed. Each auto-refresh command causes the IC to implement a respective auto-refresh cycle during which the IC refreshes the cells in the addressed row and increments or decrements the counter by one. After all of the rows have been refreshed, the counter "turns over" so that the IC can continue to refresh the rows.
To insure that the system issues auto-refresh commands frequently enough to prevent the memory cells from losing their respective data, the IC manufacturer specifies the maximum refresh period that can elapse between successive refreshes of a memory cell. For example, suppose that the IC must refresh each memory cell at least once every 64 milliseconds (ms), includes 4,096 (4 k) rows of memory cells, and refreshes an entire row during each refresh cycle. Then, to insure that no memory cells lose their respective data, the system must execute at least 4,096 auto-refresh commands (one for each row) every 64 ms. The system can issue these auto-refresh commands all at once (burst auto refresh), or can distribute them over the 64 ms refresh period (distributed auto refresh).
Furthermore, to insure that the refresh cycles are long enough to allow the IC to adequately refresh a memory cell, the IC manufacture specifies the minimum duration that the system must allow for each refresh cycle. Therefore, once the system issues an auto-refresh command, it must wait at least this minimum duration before issuing another command to the IC. For example, if the IC takes 70 nanoseconds (ns) to implement a refresh cycle, then the system must wait at least 70 ns after issuing an auto-refresh command before issuing another command to the IC.
To increase the speed rating--and thus the price--of the IC, the manufacturer often specifies the shortest possible duration for each refresh cycle. Often, this duration is too short to allow the IC to refresh a memory cell to its full signal level. As discussed below, this may require the IC manufacturer to specify a shorter refresh period between successive refreshes of a memory cell. Also as discussed below, a shorter refresh period requires the memory to issue internal refresh commands more frequently during the self-refresh mode, and thus may cause the IC to draw more power during a self-refresh mode.
FIG. 1 is a plot of the broken-line charge/discharge curves 10 and 12 for a memory cell that the IC only partially refreshes. That is, the IC implements a refresh cycle that is too short to allow the memory cell to acquire a full signal level. In this example, Vdd/2 is the threshold level between logic 1 and logic 0. Referring to the curve 10, at time t1, a memory cell storing a logic 1--which here corresponds to Vdd--is coupled to the respective digit line to begin the refresh cycle. Because the digit line is capacitive, the cell voltage drops and the digit-line voltage--which is represented by the solid curve 11--rises to a starting voltage Vs1. Furthermore, because the digit-line capacitance is approximately five times greater than the cell capacitance, the cell voltage drops more than the digit-line voltage rises. Starting at time t2, the IC charges the memory cell over a refresh time Trefresh. Typically, Trefresh is a portion of the total refresh-cycle time. For example, if the refresh-cycle time is 70 ns, Trefresh may be 60 ns. As shown, Trefresh isn't long enough for the IC to fully charge the memory cell to Vdd. Consequently, the IC can only partially charge the memory cell to V1, which is lower than Vdd. For example, V1 may be 100-300 millivolts (mV) lower than Vdd. After Trefresh elapses, the memory cell discharges to Vdd/2 over a discharge time Tdischarge, which is proportional to V1. Thus, the higher V1, the longer Tdischarge, and the lower V1, the shorter Tdischarge. The shorter Tdischarge, the more frequently the IC must refresh the signal level stored in the memory cell, and thus the shorter the maximum refresh period that the IC manufacturer can specify. A similar analysis applies to the curves 12 and 13, which corresponds to the memory cell storing logic 0.
During low-power operation of the system such as during a "sleep" mode, the system issues a self-refresh command that causes the IC to enter a self-refresh mode. During a self-refresh mode--which is typically a low-power mode of the IC--the IC typically ignores all system commands (other than a "wake-up" command) and performs few if any functions other than automatically refreshing the memory cells. Because it ignores auto-refresh commands during the self-refresh mode, the IC includes self-refresh circuitry that automatically implements self-refresh cycles during the self-refresh mode. Except for the automatic implementation, the self-refresh cycles are similar to auto-refresh cycles.
FIG. 2 is a plot of the peak and average currents that the IC draws during a self-refresh mode. The peak current Ipeak is the total refresh current that the IC draws during a respective self-refresh cycle to recharge the memory cell or cells being refreshed. Each self-refresh cycle has the refresh time Trefresh during which the IC draws the refresh current. And in this example, the self-refresh cycles are evenly distributed throughout the self-refresh period, one every Trefper seconds. For example, Trefresh=60 ns and Trefper=20 microseconds (.mu.s). The average current lavg is proportional to Ipeak, Trefresh, and the IC's power consumption, and is inversely proportional to Trefper.
To save power in the self-refresh mode, the IC designers often reduce the average current lavg by designing the IC to implement the longest possible self-refresh period between successive self-refreshes of a memory cell. Typically, the designers can lengthen the self-refresh period beyond the specified auto-refresh period, and thus can lengthen Trefper beyond the maximum time specified between evenly distributed auto-refresh cycles. For example, using the above values, if the specified maximum auto-refresh period is 64 ms, then an evenly distributed auto refresh requires one auto-refresh cycle every (64 ms/4096 rows)=15.6 .mu.s. The designers, however, may design the IC such that the self-refresh period is approximately 82 ms, which corresponds to Trefper--20 .mu.s during a self-refresh mode.
Unfortunately, because during normal operation the short auto-refresh cycles prevent the IC from fully refreshing the stored data, the IC designers cannot further lengthen Trefper without risking data corruption during the self-refresh mode.